This invention relates to a signal delay device a delay time of which can be controlled easily.
Known in the art of a signal delay circuit are various circuits such, for example, as a physical delay line, a distributed constant circuit, a bucket-brigade device (BBD), a charge-coupled device (CCD), and a shift register and a program control utilizing a random-access memory (RAM) in a digital system.
In various circuits to which a signal delay circuit is applied, there is a technical demand for arbitrarily varying a delay time of the delay circuit. Such arbitrary variation of the delay time can hardly be achieved by a delay line or a distributed constant circuit and, for this purpose, a bucket-brigade device, a charge-coupled device, a shift register or like device which uses a clock pulse for transmission of a signal is generally employed to control the frequency of the clock pulse.
In such delay system utilizing a clock pulse for transmission of a signal, a signal is sampled by a clock pulse and, accordingly, resolution of the system along the time axis is determined by the clock period. As a result, in a case where, for example, a pulse frequency modulation signal containing analog data along the time axis is to be delayed, a phase error tends to occur in the delay output. This defect can theoretically be eliminated by employing a very fast clock and thereby improving the resolution. This requires, however, increase in the number of stages of a delay element such as a bucket-brigade device, a charge-coupled device or a shift register with resulting difficulties in the circuit design and increase in the manufacturing costs.
It is, therefore, a first object of the invention to provide a signal delay device a delay time of which can be readily controlled without causing a phase error.
For achieving this object, the invention utilizes the phenomena that a CMOS gate has a delay time between its input and output terminals and this delay time changes depending upon voltage applied thereto.
The delay time of the CMOS gate depends upon power voltage and temperature. The smaller the power voltage, the longer the delay time and the larger the rate of change. As to the temperature, the higher the temperature, the longer the delay time. This is because conductance of the element of the CMOS gate changes due to the power voltage and temperature. Since dependency of the delay time upon the power voltage and temperature is too large to be ignored and influences of these factors are observed as instability in the oscillation period in an oscillation circuit and increase in distortion in the transmission system, it has been difficult to use the CMOS gate as a delay circuit in a circuit which requires a precision control. For overcoming such difficulty, it is conceivable to use a strictly stabilized power source and provide the CMOS gate in a thermostatic oven. This will however require a bulky and costly circuitry.
It is, therefore, a second object of the invention to provide a delay time stabilizing circuit capable of accurately stabilizing the delay time of the delay circuit utilizing the CMOS gate with a simple construction.
The above described delay circuit utilizing the CMOS gate is applicable to various circuits and devices. One of them is an analog delay circuit.
As described above, the prior art analog delay circuit using a bucket-brigade device, a charge-coupled device, a shift register or the like device uses a clock pulse for transmitting a signal. Since a signal is sampled by a clock pulse in this type of delay circuit, resolution in the time axis is determined by the clock period with a result that the distortion factor increases. Further, although the delay time can be changed by changing the clock period in this type of delay circuit, resolution also is caused to change with the change of the clock period.
It is, therefore, a third object of the invention to provide an analog delay circuit capable of delaying an analog signal with a high resolution and a low distortion factor and also capable of changing the delay time continuously without changing the resolution by employing the delay circuit using the CMOS gate.